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• #15837 stratova veterán Oliverda #15833

  Új Válasz 2016-02-04 11:13:46 #15837

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  stratova

  veterán

  válasz Oliverda #15833 üzenetére

  Miben nem vág össze ez pl. ezzel:

  The changes in the L2 caches and manufacturing process have done horrible things to the Fmax in Carrizo.
  The fused Pb0 (3400MHz) voltage for this specimen is 1.33750V, which is rather high.

  To operate at 3400MHz the CPU requires <1.225V(*), however at 3600MHz the minimum voltage is already at 1.3125V. A voltage curve this steep clearly shows that either the design or the manufacturing process itself is already at it´s limits. All of the 15h designs are Fmax limited by the L2 cache, so most likely in this case it is a design limit rather than a manufacturing process limit. In Excavator the L2 cache latency was reduced from 20 cycles in Piledriver or 19 cycles in Steamroller to 17 cycles.
  ...

  AMD has extremely conservative infrastructure / platform specifications in general, however for mobile products they are absolutely ridiculous.
  On FP4 platform the allowed load-line margin is 61.5% higher than on AM3+ or FM2+. On APUs especially this makes no sense, since every APU since Trinity has used SVI2 compliant voltage interface. All voltage regulators complying with SVI2 standard support load-line adjustment, so having a loose specification cannot be the result of trying to bring the motherboard component costs down.

  If AMD would cut their load-line specification on FP4 platform even to half, they could achieve some power savings in idle to low load conditions.

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